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cpldfit:  version O.76xd                            Xilinx Inc.
                                  Fitter Report
Design Name: CPLD                                Date:  1-16-2012,  6:00PM
Device Used: XC2C32A-4-QFG32
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
5  /32  ( 16%) 0   /112  (  0%) 0   /80   (  0%) 0  /32  (  0%) 5  /21  ( 24%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1       5/16      0/40     0/56     5/10    0/1      0/1      0/1      0/1
FB2       0/16      0/40     0/56     0/10    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total     5/32      0/80     0/112    5/20    0/2      0/2      0/2      0/2 

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         DGE         
Used/Tot    Used/Tot    Used/Tot    Used/Tot    
0/3         0/1         0/4         0/0


** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
                                    |  I                :     0      1
Input         :    0           0    |  I/O              :     0     12
Output        :    5           5    |  GCK/IO           :     0      3
Bidirectional :    0           0    |  GTS/IO           :     4      4
GCK           :    0           0    |  GSR/IO           :     1      1
GTS           :    0           0    |  
GSR           :    0           0    |  
                 ----        ----
        Total      5           5

End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'CPLD.ise'.
WARNING:Cpld:1006 - Design 'CPLD' has no inputs.
*************************  Summary of Mapped Logic  ************************

** 5 Outputs **

Signal              Total Total Bank Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                Pts   Inps               No.   Type      Use     STD      Style     Rate Use     State
ADDR0               0     0     2    FB1_4   3     GTS/I/O   O       LVCMOS18           FAST         
ADDR1               0     0     2    FB1_5   2     GTS/I/O   O       LVCMOS18           FAST         
BANK0               0     0     2    FB1_6   1     GTS/I/O   O       LVCMOS18           FAST         
BANK1               0     0     2    FB1_7   32    GTS/I/O   O       LVCMOS18           FAST         
MAPRAM              0     0     2    FB1_8   31    GSR/I/O   O       LVCMOS18           FAST         

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB1_1        (b)           
(unused)                      0     FB1_2        (b)           
(unused)                      0     FB1_3        (b)           
ADDR0                         0     FB1_4   3    GTS/I/O O                 
ADDR1                         0     FB1_5   2    GTS/I/O O                 
BANK0                         0     FB1_6   1    GTS/I/O O                 
BANK1                         0     FB1_7   32   GTS/I/O O                 
MAPRAM                        0     FB1_8   31   GSR/I/O O                 
(unused)                      0     FB1_9   30   I/O           
(unused)                      0     FB1_10  29   I/O           
(unused)                      0     FB1_11  28   I/O           
(unused)                      0     FB1_12  24   I/O           
(unused)                      0     FB1_13       (b)           
(unused)                      0     FB1_14  23   I/O           
(unused)                      0     FB1_15       (b)           
(unused)                      0     FB1_16       (b)           

Signals Used by Logic in Function Block

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
ADDR0             ........................................ 0       
ADDR1             ........................................ 0       
BANK0             ........................................ 0       
BANK1             ........................................ 0       
MAPRAM            ........................................ 0       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB2_1   5    I/O           
(unused)                      0     FB2_2        (b)           
(unused)                      0     FB2_3        (b)           
(unused)                      0     FB2_4        (b)           
(unused)                      0     FB2_5   6    GCK/I/O       
(unused)                      0     FB2_6   7    GCK/I/O       
(unused)                      0     FB2_7   8    GCK/I/O       
(unused)                      0     FB2_8   9    I/O           
(unused)                      0     FB2_9   10   I/O           
(unused)                      0     FB2_10       (b)           
(unused)                      0     FB2_11       (b)           
(unused)                      0     FB2_12  13   I/O           
(unused)                      0     FB2_13  17   I/O           
(unused)                      0     FB2_14  18   I/O           
(unused)                      0     FB2_15  19   I/O           
(unused)                      0     FB2_16       (b)           
*******************************  Equations  ********************************

********** Mapped Logic **********


ADDR0 <= '0';


ADDR1 <= '0';


BANK0 <= '0';


BANK1 <= '0';


MAPRAM <= '0';


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C32A-4-QFG32


   -----------------------  
  /9  10 11 12 13 14 15 16 \
 | 8                    17 | 
 | 7                    18 | 
 | 6                    19 | 
 | 5                    20 | 
 | 4    XC2C32A-4-QFG32 21 | 
 | 3                    22 | 
 | 2                    23 | 
 | 1                    24 | 
 \ 32 31 30 29 28 27 26 25 /
   -----------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 BANK0                            17 KPR                           
  2 ADDR1                            18 KPR                           
  3 ADDR0                            19 KPR                           
  4 VCCAUX                           20 VCC                           
  5 KPR                              21 GND                           
  6 KPR                              22 KPR                           
  7 KPR                              23 KPR                           
  8 KPR                              24 KPR                           
  9 KPR                              25 TDO                           
 10 KPR                              26 GND                           
 11 GND                              27 VCCIO-1.8                     
 12 VCCIO-UNUSED                     28 KPR                           
 13 KPR                              29 KPR                           
 14 TDI                              30 KPR                           
 15 TMS                              31 MAPRAM                        
 16 TCK                              32 BANK1                         


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c*-*-*
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28
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